PDL for FM0+  Version1.0
Peripheral Driverl Library for FM0+
C:/pdl_v10/library/driver/lpm/lpm.c
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00001 /*******************************************************************************
00002 * Copyright (C) 2013 Spansion LLC. All Rights Reserved. 
00003 *
00004 * This software is owned and published by: 
00005 * Spansion LLC, 915 DeGuigne Dr. Sunnyvale, CA  94088-3453 ("Spansion").
00006 *
00007 * BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND 
00008 * BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT.
00009 *
00010 * This software contains source code for use with Spansion 
00011 * components. This software is licensed by Spansion to be adapted only 
00012 * for use in systems utilizing Spansion components. Spansion shall not be 
00013 * responsible for misuse or illegal use of this software for devices not 
00014 * supported herein.  Spansion is providing this software "AS IS" and will 
00015 * not be responsible for issues arising from incorrect user implementation 
00016 * of the software.  
00017 *
00018 * SPANSION MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE,
00019 * REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), 
00020 * ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, 
00021 * WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED 
00022 * WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED 
00023 * WARRANTY OF NONINFRINGEMENT.  
00024 * SPANSION SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, 
00025 * NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT 
00026 * LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, 
00027 * LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR 
00028 * INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, 
00029 * INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, 
00030 * SAVINGS OR PROFITS, 
00031 * EVEN IF SPANSION HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. 
00032 * YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR
00033 * INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED 
00034 * FROM, THE SOFTWARE.  
00035 *
00036 * This software may be replicated in part or whole for the licensed use, 
00037 * with the restriction that this Disclaimer and Copyright notice must be 
00038 * included with each copy of this software, whether used in part or whole, 
00039 * at all times.  
00040 */
00041 /******************************************************************************/
00053 /******************************************************************************/
00054 /* Include files                                                              */
00055 /******************************************************************************/
00056 #include "lpm.h"
00057 
00058 #if (defined(PDL_PERIPHERAL_LPM_ACTIVE))
00059 
00065 
00066 /******************************************************************************/
00067 /* Local pre-processor symbols/macros ('#define')                             */
00068 /******************************************************************************/
00069 
00070 /******************************************************************************/
00071 /* Global variable definitions (declared in header file with 'extern')        */
00072 /******************************************************************************/
00073 
00074 /******************************************************************************/
00075 /* Local type definitions ('typedef')                                         */
00076 /******************************************************************************/
00077 
00078 /******************************************************************************/
00079 /* Local function prototypes ('static')                                       */
00080 /******************************************************************************/
00081 
00082 /******************************************************************************/
00083 /* Local variable definitions ('static')                                      */
00084 /******************************************************************************/
00085 
00086 /******************************************************************************/
00087 /* Function implementation - global ('extern') and local ('static')           */
00088 /******************************************************************************/
00089 // SCR address
00090 #define CM0P_CORE_CSR  *((volatile unsigned int*)(0xE000ED10UL))
00091    
00092 // Backup registers base address   
00093 #define LPCM_BACKUP_REG_BASE   ((volatile uint8_t*)0x40035900)
00094    
00095 /*---------------------------------------------------------------------------*/
00096 /* local datatypes                                                           */
00097 /*---------------------------------------------------------------------------*/
00098 
00099 /*---------------------------------------------------------------------------*/
00100 /* local data                                                                */
00101 /*---------------------------------------------------------------------------*/
00102 
00103 /*---------------------------------------------------------------------------*/
00104 /* global data                                                               */
00105 /*---------------------------------------------------------------------------*/
00106 
00107 /*---------------------------------------------------------------------------*/
00108 /* global functions                                                          */
00109 /*---------------------------------------------------------------------------*/
00110 
00116 static uint16_t WRFSRDummyRead(void)
00117 {
00118     uint16_t Dummy;
00119     Dummy = FM0P_DS->WRFSR;
00120     return Dummy;
00121 }
00122 
00128 static uint16_t WIFSRDummyRead(void)
00129 {
00130     uint16_t Dummy;
00131     Dummy = FM0P_DS->WIFSR;
00132     return Dummy;
00133 }
00134 
00135 
00155 void Lpm_GoToStandByMode(en_lpm_mode_t enMode, boolean_t bIoRemain)
00156 {
00157     WRFSRDummyRead();
00158     WIFSRDummyRead();
00159     switch (enMode)
00160     {
00161         case StbSleepMode:
00162             CM0P_CORE_CSR &= 0xFFFFFFFFB;
00163             __WFI();
00164             break;
00165         case StbTimerMode:
00166             if( bIoRemain == 0 )
00167             {
00168                 FM0P_CRG->STB_CTL = 0x1ACC0000;
00169             }
00170             else
00171             {
00172                 FM0P_CRG->STB_CTL = 0x1ACC0010;
00173             }
00174             CM0P_CORE_CSR |= 0x00000004;
00175             __WFI();
00176             break;
00177         case StbStopMode:
00178             FM0P_DS->PMD_CTL &= ~0x01; /* RTCE=0 */
00179             if( bIoRemain == 0 )
00180             {
00181                 FM0P_CRG->STB_CTL = 0x1ACC0002;
00182             }
00183             else
00184             {
00185                 FM0P_CRG->STB_CTL = 0x1ACC0012;
00186             }
00187             CM0P_CORE_CSR |= 0x00000004;
00188             __WFI();
00189             break;    
00190         case StbRtcMode:
00191             FM0P_DS->PMD_CTL |= 0x01; /* RTCE=1 */
00192             if( bIoRemain == 0 )
00193             {
00194                 FM0P_CRG->STB_CTL = 0x1ACC0002;
00195             }
00196             else
00197             {
00198                 FM0P_CRG->STB_CTL = 0x1ACC0012;
00199             }
00200             CM0P_CORE_CSR |= 0x00000004;
00201             __WFI();
00202             break;
00203         case DeepStbRtcMode: 
00204             FM0P_DS->PMD_CTL |= 0x01; /* RTCE=1 */
00205             if( bIoRemain == 0 )
00206             {
00207                 FM0P_CRG->STB_CTL = 0x1ACC0006;
00208             }
00209             else
00210             {
00211                 FM0P_CRG->STB_CTL = 0x1ACC0016;
00212             }
00213             CM0P_CORE_CSR |= 0x00000004;
00214             __WFI();
00215             break;
00216         case DeepStbStopMode:
00217             FM0P_DS->PMD_CTL &= ~0x01; /* RTCE=0 */
00218             if( bIoRemain == 0 )
00219             {
00220                 FM0P_CRG->STB_CTL = 0x1ACC0006;
00221             }
00222             else
00223             {
00224                 FM0P_CRG->STB_CTL = 0x1ACC0016;
00225             }
00226             CM0P_CORE_CSR |= 0x00000004;
00227             __WFI();
00228             break;                       
00229         default:
00230             break;
00231     }
00232 }
00233 
00246 en_result_t Lpm_ConfigDeepStbRetCause(stc_dstb_ret_cause_t* pstcCause)
00247 {
00248     if(pstcCause->bRtcEn == 1)
00249     {
00250         bFM0P_DS_WIER_WRTCE = 1;
00251     }
00252     else
00253     {
00254         bFM0P_DS_WIER_WRTCE = 0;
00255     }
00256     
00257     if(pstcCause->bLvdEn == 1)
00258     {
00259         bFM0P_DS_WIER_WLVDE = 1;
00260     }
00261     else
00262     {
00263         bFM0P_DS_WIER_WLVDE = 0;
00264     }
00265     
00266     if(pstcCause->bWakeup1En == 1)
00267     {
00268         bFM0P_DS_WIER_WUE1 = 1;
00269     }
00270     else
00271     {
00272         bFM0P_DS_WIER_WUE1 = 0;
00273     }
00274     
00275     if(pstcCause->bWakeup2En == 1)
00276     {
00277         bFM0P_DS_WIER_WUE2 = 1;
00278     }
00279     else
00280     {
00281         bFM0P_DS_WIER_WUE2 = 0;
00282     }
00283     
00284     if(pstcCause->bWakeup3En == 1)
00285     {
00286         bFM0P_DS_WIER_WUE3 = 1;
00287     }
00288     else
00289     {
00290         bFM0P_DS_WIER_WUE3 = 0;
00291     }
00292     
00293     if(pstcCause->bWakeup4En == 1)
00294     {
00295         bFM0P_DS_WIER_WUE4 = 1;
00296     }
00297     else
00298     {
00299         bFM0P_DS_WIER_WUE4 = 0;
00300     }
00301     
00302     if(pstcCause->bWakeup5En == 1)
00303     {
00304         bFM0P_DS_WIER_WUE5 = 1;
00305     }
00306     else
00307     {
00308         bFM0P_DS_WIER_WUE5 = 0;
00309     }
00310     
00311     if(pstcCause->bCec0En == 1)
00312     {
00313         bFM0P_DS_WIER_WCEC0E = 1;
00314     }
00315     else
00316     {
00317         bFM0P_DS_WIER_WCEC0E = 0;
00318     }
00319     
00320     if(pstcCause->bCec1En == 1)
00321     {
00322         bFM0P_DS_WIER_WCEC1E = 1;
00323     }
00324     else
00325     {
00326         bFM0P_DS_WIER_WCEC1E = 0;
00327     }
00328     
00329     return Ok;
00330 }
00331 
00351 en_dstb_ret_cause_t Lpm_ReadDeepStbRetCause(void)
00352 {
00353     uint16_t rWIFSR,rWRFSR;
00354     rWRFSR = FM0P_DS->WRFSR;
00355     rWIFSR = FM0P_DS->WIFSR;
00356     
00357     if(rWRFSR & WRFSR_WINITX)
00358     {
00359         return DeepStbInitx;
00360     }
00361     
00362     if(rWRFSR & WIFSR_WLVDI)
00363     {
00364         return DeepStbLvdReset;
00365     }
00366     
00367     if(rWIFSR & WIFSR_WRTCI)
00368     {
00369         return DeepStbRtcInt;
00370     }
00371     else if(rWIFSR & WIFSR_WLVDI)
00372     {
00373         return DeepStbLvdInt;
00374     }
00375     else if(rWIFSR & WIFSR_WUI0)
00376     {
00377         return DeepStbWkupPin0;
00378     }
00379     else if(rWIFSR & WIFSR_WUI1)
00380     {
00381         return DeepStbWkupPin1;
00382     }
00383     else if(rWIFSR & WIFSR_WUI2)
00384     {
00385         return DeepStbWkupPin2;
00386     }
00387     else if(rWIFSR & WIFSR_WUI3)
00388     {
00389         return DeepStbWkupPin3;
00390     }
00391     else if(rWIFSR & WIFSR_WUI4)
00392     {
00393         return DeepStbWkupPin4;
00394     }
00395     else if(rWIFSR & WIFSR_WUI5)
00396     {
00397         return DeepStbWkupPin5;
00398     }
00399     else if(rWIFSR & WIFSR_WCEC0I)
00400     {
00401         return DeepStbCec0;
00402     }
00403     else if(rWIFSR & WIFSR_WCEC1I)
00404     {
00405         return DeepStbCec1;
00406     }
00407     return DeepStbNoFlag;
00408 }
00409 
00429 en_result_t Lpm_SetWkupPinLevel(en_dstb_wkup_pin_t enPinIndex, en_wkup_valid_level_t enLevel)
00430 {
00431     if(enPinIndex > WkupPin5)
00432     {
00433         return ErrorInvalidParameter;
00434     }
00435   
00436     FM0P_DS->WILVR &= ~(1ul << enPinIndex);
00437     FM0P_DS->WILVR |= ((uint8_t)enLevel << enPinIndex);
00438     
00439     return Ok;
00440 }
00441 
00470 en_result_t Lpm_WriteBackupReg(en_dstb_bakup_reg_t enRegIndex, uint8_t u8Data)
00471 {
00472     if(enRegIndex > BackupReg15)
00473     {
00474         return ErrorInvalidParameter;
00475     }
00476   
00477     *(uint8_t*)(LPCM_BACKUP_REG_BASE + (uint8_t)enRegIndex) = u8Data;
00478     return Ok;
00479 }
00480 
00507 uint8_t Lpm_ReadBackupReg(en_dstb_bakup_reg_t enRegIndex)
00508 {
00509     return *(uint8_t*)(LPCM_BACKUP_REG_BASE + (uint8_t)enRegIndex);
00510 }
00511 
00526 en_result_t Lpm_ConfigSubClk(boolean_t bSupplyCec, boolean_t bSupplyRtc)
00527 {
00528     if(bSupplyCec == TRUE)
00529     {
00530         bFM0P_DS_RCK_CTL_CECCKE = 1;
00531     }
00532     else
00533     {
00534         bFM0P_DS_RCK_CTL_CECCKE = 0;
00535     }
00536     
00537     if(bSupplyRtc == TRUE)
00538     {
00539         bFM0P_DS_RCK_CTL_RTCCKE = 1;
00540     }
00541     else
00542     {
00543         bFM0P_DS_RCK_CTL_RTCCKE = 0;
00544     }
00545     
00546     return Ok;
00547 }
00548 
00562 en_result_t Lpm_ConfigDeepStbRAMRetention(boolean_t bRamRetain)
00563 {
00564     if(bRamRetain == FALSE)
00565     {
00566         FM0P_DS->DSRAMR &= ~0x03u; 
00567     }
00568     else
00569     {
00570         FM0P_DS->DSRAMR |= 0x03u; 
00571     }
00572     return Ok;
00573 }
00574 
00576 
00577 #endif // #if (defined(PDL_PERIPHERAL_ENABLE_LPM))
00578 
00579 /******************************************************************************/
00580 /* EOF (not truncated)                                                        */
00581 /******************************************************************************/