PDL for FM0+  Version1.0
Peripheral Driverl Library for FM0+
C:/pdl_v10/library/driver/interrupts.c
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00001 /*******************************************************************************
00002 * Copyright (C) 2013 Spansion LLC. All Rights Reserved. 
00003 *
00004 * This software is owned and published by: 
00005 * Spansion LLC, 915 DeGuigne Dr. Sunnyvale, CA  94088-3453 ("Spansion").
00006 *
00007 * BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND 
00008 * BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT.
00009 *
00010 * This software contains source code for use with Spansion 
00011 * components. This software is licensed by Spansion to be adapted only 
00012 * for use in systems utilizing Spansion components. Spansion shall not be 
00013 * responsible for misuse or illegal use of this software for devices not 
00014 * supported herein.  Spansion is providing this software "AS IS" and will 
00015 * not be responsible for issues arising from incorrect user implementation 
00016 * of the software.  
00017 *
00018 * SPANSION MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE,
00019 * REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), 
00020 * ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, 
00021 * WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED 
00022 * WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED 
00023 * WARRANTY OF NONINFRINGEMENT.  
00024 * SPANSION SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, 
00025 * NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT 
00026 * LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, 
00027 * LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR 
00028 * INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, 
00029 * INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, 
00030 * SAVINGS OR PROFITS, 
00031 * EVEN IF SPANSION HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. 
00032 * YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR
00033 * INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED 
00034 * FROM, THE SOFTWARE.  
00035 *
00036 * This software may be replicated in part or whole for the licensed use, 
00037 * with the restriction that this Disclaimer and Copyright notice must be 
00038 * included with each copy of this software, whether used in part or whole, 
00039 * at all times.  
00040 */
00041 /******************************************************************************/
00054 /******************************************************************************/
00055 /* Include files                                                              */
00056 /******************************************************************************/
00057 #include "interrupts.h"
00058 
00059 /******************************************************************************/
00060 /*********************************** NMI **************************************/
00061 /******************************************************************************/
00062 #if (PDL_INTERRUPT_ENABLE_NMI == PDL_ON) || (PDL_INTERRUPT_ENABLE_HWWDG == PDL_ON)
00063 void NMI_Handler(void)
00064 {
00065 #if (PDL_INTERRUPT_ENABLE_NMI == PDL_ON)
00066     if(bFM0P_INTREQ_EXC02MON_NMI)
00067     {
00068         Nmi_IrqHandler();
00069     }
00070 #endif
00071 #if (PDL_INTERRUPT_ENABLE_HWWDG == PDL_ON)
00072     if (bFM0P_INTREQ_EXC02MON_HWINT == 1u)
00073     {
00074         HwwdgIrqHandler();
00075     }
00076 #endif
00077 }
00078 #endif
00079 
00080 /******************************************************************************/
00081 /******************************* SW watchdog **********************************/
00082 /******************************************************************************/
00083 #if (PDL_INTERRUPT_ENABLE_SWWDG == PDL_ON)
00084 void SWDT_IRQHandler(void)
00085 {
00086     SwwdgIrqHandler();
00087 }
00088 #endif
00089 
00090 /******************************************************************************/
00091 /*********************************** ADC **************************************/
00092 /******************************************************************************/
00093 #if (PDL_INTERRUPT_ENABLE_ADC0 == PDL_ON) 
00094 void ADC0_IRQHandler(void)
00095 {
00096     AdcIrqHandler((volatile stc_adcn_t*)&ADC0, &(m_astcAdcInstanceDataLut[AdcInstanceIndexAdc0].stcInternData));
00097 }
00098 #endif
00099 
00100 #if (PDL_INTERRUPT_ENABLE_ADC1 == PDL_ON) 
00101 void ADC1_IRQHandler(void)
00102 {
00103     AdcIrqHandler((volatile stc_adcn_t*)&ADC1, &(m_astcAdcInstanceDataLut[AdcInstanceIndexAdc1].stcInternData));
00104 }
00105 #endif
00106 
00107 #if (PDL_INTERRUPT_ENABLE_LCD == PDL_ON) || (PDL_INTERRUPT_ENABLE_ADC2 == PDL_ON) 
00108 void ADC2_LCD_IRQHandler(void)
00109 {
00110 #if (PDL_INTERRUPT_ENABLE_LCD == PDL_ON)
00111 #endif
00112 #if (PDL_INTERRUPT_ENABLE_ADC2 == PDL_ON)   
00113     AdcIrqHandler((volatile stc_adcn_t*)&ADC2, &(m_astcAdcInstanceDataLut[AdcInstanceIndexAdc2].stcInternData));
00114 #endif    
00115 }
00116 #endif
00117 
00118 /******************************************************************************/
00119 /*********************************** BT/Flash *********************************/
00120 /******************************************************************************/
00121 
00122 #if (PDL_INTERRUPT_ENABLE_BT0 == PDL_ON) || \
00123     (PDL_INTERRUPT_ENABLE_BT1 == PDL_ON) || \
00124     (PDL_INTERRUPT_ENABLE_BT2 == PDL_ON) || \
00125     (PDL_INTERRUPT_ENABLE_BT3 == PDL_ON) || \
00126     (PDL_INTERRUPT_ENABLE_BT4 == PDL_ON) || \
00127     (PDL_INTERRUPT_ENABLE_BT5 == PDL_ON) || \
00128     (PDL_INTERRUPT_ENABLE_BT6 == PDL_ON) || \
00129     (PDL_INTERRUPT_ENABLE_BT7 == PDL_ON) || \
00130     (PDL_INTERRUPT_ENABLE_FLASH == PDL_ON)  
00131 
00136 void BT0_7_FLASH_IRQHandler(void)
00137 {
00138     uint32_t u32IrqMon = FM0P_INTREQ->IRQ31MON;
00139   
00140 #if (PDL_INTERRUPT_ENABLE_BT0 == PDL_ON) 
00141     if(0 != (u32IrqMon & 0x00000003ul))
00142     {
00143         Bt_IrqHandler((volatile stc_btn_t*)&BT0, &m_astcBtInstanceDataLut[BtInstanceIndexBt0].stcInternData);
00144     }
00145 #endif     
00146 #if (PDL_INTERRUPT_ENABLE_BT1 == PDL_ON) 
00147     if(0 != (u32IrqMon & 0x0000000Cul))
00148     {
00149         Bt_IrqHandler((volatile stc_btn_t*)&BT1, &m_astcBtInstanceDataLut[BtInstanceIndexBt1].stcInternData);
00150     }
00151 #endif     
00152 #if (PDL_INTERRUPT_ENABLE_BT2 == PDL_ON) 
00153     if(0 != (u32IrqMon & 0x00000030ul))
00154     {
00155         Bt_IrqHandler((volatile stc_btn_t*)&BT2, &m_astcBtInstanceDataLut[BtInstanceIndexBt2].stcInternData);
00156     }
00157 #endif 
00158 #if (PDL_INTERRUPT_ENABLE_BT3 == PDL_ON) 
00159     if(0 != (u32IrqMon & 0x000000C0ul))
00160     {
00161         Bt_IrqHandler((volatile stc_btn_t*)&BT3, &m_astcBtInstanceDataLut[BtInstanceIndexBt3].stcInternData);
00162     }
00163 #endif    
00164 #if (PDL_INTERRUPT_ENABLE_BT4 == PDL_ON) 
00165     if(0 != (u32IrqMon & 0x00000300ul))
00166     {
00167         Bt_IrqHandler((volatile stc_btn_t*)&BT4, &m_astcBtInstanceDataLut[BtInstanceIndexBt4].stcInternData);
00168     }
00169 #endif
00170 #if (PDL_INTERRUPT_ENABLE_BT5 == PDL_ON) 
00171     if(0 != (u32IrqMon & 0x00000C00ul))
00172     {
00173         Bt_IrqHandler((volatile stc_btn_t*)&BT5, &m_astcBtInstanceDataLut[BtInstanceIndexBt5].stcInternData);
00174     }
00175 #endif  
00176 #if (PDL_INTERRUPT_ENABLE_BT6 == PDL_ON) 
00177     if(0 != (u32IrqMon & 0x00003000ul))
00178     {
00179         Bt_IrqHandler((volatile stc_btn_t*)&BT6, &m_astcBtInstanceDataLut[BtInstanceIndexBt6].stcInternData);
00180     }
00181 #endif
00182 #if (PDL_INTERRUPT_ENABLE_BT7 == PDL_ON) 
00183     if(0 != (u32IrqMon & 0x0000C000ul))
00184     {
00185         Bt_IrqHandler((volatile stc_btn_t*)&BT7, &m_astcBtInstanceDataLut[BtInstanceIndexBt7].stcInternData);
00186     }
00187 #endif   
00188 #if (PDL_INTERRUPT_ENABLE_FLASH == PDL_OFF)
00189 #endif    
00190 }
00191 #endif
00192 
00193 /******************************************************************************/
00194 /*********************************** CLK/WC/RTC *******************************/
00195 /******************************************************************************/
00196 #if (PDL_INTERRUPT_ENABLE_CLK == PDL_ON) || \
00197     (PDL_INTERRUPT_ENABLE_WC == PDL_ON) || \
00198     (PDL_INTERRUPT_ENABLE_RTC == PDL_ON)
00199 void TIM_IRQHandler(void)
00200 {
00201     uint32_t u32IrqMon = FM0P_INTREQ->IRQ24MON;
00202 
00203 #if (PDL_INTERRUPT_ENABLE_RTC == PDL_ON)
00204     if(0 != (u32IrqMon & 0x00000020ul))
00205     {  
00206         Rtc_IrqHandler();
00207     }
00208 #endif
00209 #if (PDL_INTERRUPT_ENABLE_WC == PDL_ON)
00210     if(0 != (u32IrqMon & 0x00000010ul))
00211     {  
00212         Wc_IrqHandler();
00213     }
00214 #endif    
00215 #if (PDL_INTERRUPT_ENABLE_CLK == PDL_ON)
00216     if(0 != (u32IrqMon & 0x00000007ul))
00217     {  
00218         Clk_IrqHandler();
00219     }
00220 #endif    
00221 }
00222 #endif
00223 
00224 /******************************************************************************/
00225 /*********************************** CSV **************************************/
00226 /******************************************************************************/
00227 #if (PDL_INTERRUPT_ENABLE_CSV == PDL_ON)
00228 void CSV_IRQHandler(void)
00229 {
00230     Csv_IrqHandler();
00231 }
00232 #endif
00233 
00234 /******************************************************************************/
00235 /******************************* Dual Timer/QPRC ******************************/
00236 /******************************************************************************/
00237 #if (PDL_INTERRUPT_ENABLE_DT == PDL_ON) || (PDL_INTERRUPT_ENABLE_QPRC0 == PDL_ON) || \
00238     (PDL_INTERRUPT_ENABLE_QPRC1 == PDL_ON) || (PDL_INTERRUPT_ENABLE_QPRC2 == PDL_ON)
00239 void DT_QPRC_Handler(void)
00240 {
00241     uint32_t u32IrqMon = FM0P_INTREQ->IRQ06MON;
00242 #if (PDL_INTERRUPT_ENABLE_DT == PDL_ON)
00243     if (0 != (u32IrqMon & 0x00000001ul))
00244     {
00245         DtIrqHandler(DtChannel0);
00246     }
00247     if (0 != (u32IrqMon & 0x00000002ul))
00248     {
00249         DtIrqHandler(DtChannel1);
00250     }
00251 #endif    
00252 #if (PDL_INTERRUPT_ENABLE_QPRC0 == PDL_ON)
00253     if(0!= (u32IrqMon & 0x000000FCul))
00254     {
00255         Qprc_IrqHandler((volatile stc_qprcn_t*)&QPRC0, &m_astcQprcInstanceDataLut[QprcInstanceIndexQprc0].stcInternData);
00256     }
00257 #endif  
00258 #if (PDL_INTERRUPT_ENABLE_QPRC1 == PDL_ON)
00259     if(0!= (u32IrqMon & 0x00003F00ul))
00260     {
00261         Qprc_IrqHandler((volatile stc_qprcn_t*)&QPRC1, &m_astcQprcInstanceDataLut[QprcInstanceIndexQprc1].stcInternData);
00262     }
00263 #endif      
00264 #if (PDL_INTERRUPT_ENABLE_QPRC2 == PDL_ON)    
00265     if(0!= (u32IrqMon & 0x000FC000ul))
00266     {
00267         Qprc_IrqHandler((volatile stc_qprcn_t*)&QPRC2, &m_astcQprcInstanceDataLut[QprcInstanceIndexQprc2].stcInternData);
00268     }
00269 #endif    
00270 }
00271 #endif
00272 
00273 /******************************************************************************/
00274 /*********************************** LVD **************************************/
00275 /******************************************************************************/
00276 #if (PDL_INTERRUPT_ENABLE_LVD == PDL_ON)
00277 
00282 void LVD_IRQHandler(void)
00283 {
00284     LvdIrqHandler();
00285 }
00286 #endif // #if (PDL_INTERRUPT_ENABLE_LVD == PDL_ON) && (PDL_PERIPHERAL_ENABLE_LVD == PDL_ON)
00287 
00288 /******************************************************************************/
00289 /********************************* EXINT **************************************/
00290 /******************************************************************************/
00291 #if (PDL_INTERRUPT_ENABLE_EXINT0 == PDL_ON) || \
00292     (PDL_INTERRUPT_ENABLE_EXINT1 == PDL_ON) || \
00293     (PDL_INTERRUPT_ENABLE_EXINT2 == PDL_ON) || \
00294     (PDL_INTERRUPT_ENABLE_EXINT3 == PDL_ON) || \
00295     (PDL_INTERRUPT_ENABLE_EXINT4 == PDL_ON) || \
00296     (PDL_INTERRUPT_ENABLE_EXINT5 == PDL_ON) || \
00297     (PDL_INTERRUPT_ENABLE_EXINT6 == PDL_ON) || \
00298     (PDL_INTERRUPT_ENABLE_EXINT7 == PDL_ON)   
00299 
00304 void INT0_7_Handler(void)
00305 { 
00306 #if(PDL_INTERRUPT_ENABLE_EXINT0 == PDL_ON)
00307     if(0 != bFM0P_INTREQ_IRQ04MON_EXTINT0)
00308     {
00309         Exint_IrqHandler(ExintInstanceIndexExint0);
00310     }
00311 #endif  
00312 #if(PDL_INTERRUPT_ENABLE_EXINT1 == PDL_ON)
00313     if(0 != bFM0P_INTREQ_IRQ04MON_EXTINT1)
00314     {
00315         Exint_IrqHandler(ExintInstanceIndexExint1);
00316     }
00317 #endif 
00318 #if(PDL_INTERRUPT_ENABLE_EXINT2 == PDL_ON)
00319     if(0 != bFM0P_INTREQ_IRQ04MON_EXTINT2)
00320     {
00321         Exint_IrqHandler(ExintInstanceIndexExint2);
00322     }
00323 #endif 
00324 #if(PDL_INTERRUPT_ENABLE_EXINT3 == PDL_ON)
00325     if(0 != bFM0P_INTREQ_IRQ04MON_EXTINT3)
00326     {
00327         Exint_IrqHandler(ExintInstanceIndexExint3);
00328     }
00329 #endif 
00330 #if(PDL_INTERRUPT_ENABLE_EXINT4 == PDL_ON)
00331     if(0 != bFM0P_INTREQ_IRQ04MON_EXTINT4)
00332     {
00333         Exint_IrqHandler(ExintInstanceIndexExint4);
00334     }
00335 #endif 
00336 #if(PDL_INTERRUPT_ENABLE_EXINT5 == PDL_ON)
00337     if(0 != bFM0P_INTREQ_IRQ04MON_EXTINT5)
00338     {
00339         Exint_IrqHandler(ExintInstanceIndexExint5);
00340     }
00341 #endif 
00342 #if(PDL_INTERRUPT_ENABLE_EXINT6 == PDL_ON)
00343     if(0 != bFM0P_INTREQ_IRQ04MON_EXTINT6)
00344     {
00345         Exint_IrqHandler(ExintInstanceIndexExint6);
00346     }
00347 #endif 
00348 #if(PDL_INTERRUPT_ENABLE_EXINT7 == PDL_ON)
00349     if(0 != bFM0P_INTREQ_IRQ04MON_EXTINT7)
00350     {
00351         Exint_IrqHandler(ExintInstanceIndexExint7);
00352     }
00353 #endif     
00354     
00355 }
00356 #endif
00357 
00358 #if (PDL_INTERRUPT_ENABLE_EXINT8 == PDL_ON) || \
00359     (PDL_INTERRUPT_ENABLE_EXINT9 == PDL_ON) || \
00360     (PDL_INTERRUPT_ENABLE_EXINT10 == PDL_ON) || \
00361     (PDL_INTERRUPT_ENABLE_EXINT11 == PDL_ON) || \
00362     (PDL_INTERRUPT_ENABLE_EXINT12 == PDL_ON) || \
00363     (PDL_INTERRUPT_ENABLE_EXINT13 == PDL_ON) || \
00364     (PDL_INTERRUPT_ENABLE_EXINT14 == PDL_ON) || \
00365     (PDL_INTERRUPT_ENABLE_EXINT15 == PDL_ON) || \
00366     (PDL_INTERRUPT_ENABLE_EXINT16 == PDL_ON) || \
00367     (PDL_INTERRUPT_ENABLE_EXINT17 == PDL_ON) || \
00368     (PDL_INTERRUPT_ENABLE_EXINT18 == PDL_ON) || \
00369     (PDL_INTERRUPT_ENABLE_EXINT19 == PDL_ON) || \
00370     (PDL_INTERRUPT_ENABLE_EXINT20 == PDL_ON) || \
00371     (PDL_INTERRUPT_ENABLE_EXINT21 == PDL_ON) || \
00372     (PDL_INTERRUPT_ENABLE_EXINT22 == PDL_ON) || \
00373     (PDL_INTERRUPT_ENABLE_EXINT23 == PDL_ON) || \
00374     (PDL_INTERRUPT_ENABLE_EXINT24 == PDL_ON) || \
00375     (PDL_INTERRUPT_ENABLE_EXINT25 == PDL_ON) || \
00376     (PDL_INTERRUPT_ENABLE_EXINT26 == PDL_ON) || \
00377     (PDL_INTERRUPT_ENABLE_EXINT27 == PDL_ON) || \
00378     (PDL_INTERRUPT_ENABLE_EXINT28 == PDL_ON) || \
00379     (PDL_INTERRUPT_ENABLE_EXINT29 == PDL_ON) || \
00380     (PDL_INTERRUPT_ENABLE_EXINT30 == PDL_ON) || \
00381     (PDL_INTERRUPT_ENABLE_EXINT31 == PDL_ON)     
00382 
00387 void INT8_31_Handler(void)
00388 { 
00389 #if(PDL_INTERRUPT_ENABLE_EXINT8 == PDL_ON)
00390     if(0 != bFM0P_INTREQ_IRQ05MON_EXTINT8)
00391     {
00392         Exint_IrqHandler(ExintInstanceIndexExint8);
00393     }
00394 #endif  
00395 #if(PDL_INTERRUPT_ENABLE_EXINT9 == PDL_ON)
00396     if(0 != bFM0P_INTREQ_IRQ05MON_EXTINT9)
00397     {
00398         Exint_IrqHandler(ExintInstanceIndexExint9);
00399     }
00400 #endif 
00401 #if(PDL_INTERRUPT_ENABLE_EXINT10 == PDL_ON)
00402     if(0 != bFM0P_INTREQ_IRQ05MON_EXTINT10)
00403     {
00404         Exint_IrqHandler(ExintInstanceIndexExint10);
00405     }
00406 #endif 
00407 #if(PDL_INTERRUPT_ENABLE_EXINT11 == PDL_ON)
00408     if(0 != bFM0P_INTREQ_IRQ05MON_EXTINT11)
00409     {
00410         Exint_IrqHandler(ExintInstanceIndexExint11);
00411     }
00412 #endif 
00413 #if(PDL_INTERRUPT_ENABLE_EXINT12 == PDL_ON)
00414     if(0 != bFM0P_INTREQ_IRQ05MON_EXTINT12)
00415     {
00416         Exint_IrqHandler(ExintInstanceIndexExint12);
00417     }
00418 #endif 
00419 #if(PDL_INTERRUPT_ENABLE_EXINT13 == PDL_ON)
00420     if(0 != bFM0P_INTREQ_IRQ05MON_EXTINT13)
00421     {
00422         Exint_IrqHandler(ExintInstanceIndexExint13);
00423     }
00424 #endif 
00425 #if(PDL_INTERRUPT_ENABLE_EXINT14 == PDL_ON)
00426     if(0 != bFM0P_INTREQ_IRQ05MON_EXTINT14)
00427     {
00428         Exint_IrqHandler(ExintInstanceIndexExint14);
00429     }
00430 #endif 
00431 #if(PDL_INTERRUPT_ENABLE_EXINT15 == PDL_ON)
00432     if(0 != bFM0P_INTREQ_IRQ05MON_EXTINT15)
00433     {
00434         Exint_IrqHandler(ExintInstanceIndexExint15);
00435     }
00436 #endif     
00437 #if(PDL_INTERRUPT_ENABLE_EXINT16 == PDL_ON)
00438     if(0 != bFM0P_INTREQ_IRQ05MON_EXTINT16)
00439     {
00440         Exint_IrqHandler(ExintInstanceIndexExint16);
00441     }
00442 #endif  
00443 #if(PDL_INTERRUPT_ENABLE_EXINT17 == PDL_ON)
00444     if(0 != bFM0P_INTREQ_IRQ05MON_EXTINT17)
00445     {
00446         Exint_IrqHandler(ExintInstanceIndexExint17);
00447     }
00448 #endif 
00449 #if(PDL_INTERRUPT_ENABLE_EXINT18 == PDL_ON)
00450     if(0 != bFM0P_INTREQ_IRQ05MON_EXTINT18)
00451     {
00452         Exint_IrqHandler(ExintInstanceIndexExint18);
00453     }
00454 #endif 
00455 #if(PDL_INTERRUPT_ENABLE_EXINT19 == PDL_ON)
00456     if(0 != bFM0P_INTREQ_IRQ05MON_EXTINT19)
00457     {
00458         Exint_IrqHandler(ExintInstanceIndexExint19);
00459     }
00460 #endif 
00461 #if(PDL_INTERRUPT_ENABLE_EXINT20 == PDL_ON)
00462     if(0 != bFM0P_INTREQ_IRQ05MON_EXTINT20)
00463     {
00464         Exint_IrqHandler(ExintInstanceIndexExint20);
00465     }
00466 #endif 
00467 #if(PDL_INTERRUPT_ENABLE_EXINT21 == PDL_ON)
00468     if(0 != bFM0P_INTREQ_IRQ05MON_EXTINT21)
00469     {
00470         Exint_IrqHandler(ExintInstanceIndexExint21);
00471     }
00472 #endif 
00473 #if(PDL_INTERRUPT_ENABLE_EXINT22 == PDL_ON)
00474     if(0 != bFM0P_INTREQ_IRQ05MON_EXTINT22)
00475     {
00476         Exint_IrqHandler(ExintInstanceIndexExint22);
00477     }
00478 #endif 
00479 #if(PDL_INTERRUPT_ENABLE_EXINT23 == PDL_ON)
00480     if(0 != bFM0P_INTREQ_IRQ05MON_EXTINT23)
00481     {
00482         Exint_IrqHandler(ExintInstanceIndexExint23);
00483     }
00484 #endif
00485 #if(PDL_INTERRUPT_ENABLE_EXINT24 == PDL_ON)
00486     if(0 != bFM0P_INTREQ_IRQ05MON_EXTINT24)
00487     {
00488         Exint_IrqHandler(ExintInstanceIndexExint24);
00489     }
00490 #endif  
00491 #if(PDL_INTERRUPT_ENABLE_EXINT25 == PDL_ON)
00492     if(0 != bFM0P_INTREQ_IRQ05MON_EXTINT25)
00493     {
00494         Exint_IrqHandler(ExintInstanceIndexExint25);
00495     }
00496 #endif 
00497 #if(PDL_INTERRUPT_ENABLE_EXINT26 == PDL_ON)
00498     if(0 != bFM0P_INTREQ_IRQ05MON_EXTINT26)
00499     {
00500         Exint_IrqHandler(ExintInstanceIndexExint26);
00501     }
00502 #endif 
00503 #if(PDL_INTERRUPT_ENABLE_EXINT27 == PDL_ON)
00504     if(0 != bFM0P_INTREQ_IRQ05MON_EXTINT27)
00505     {
00506         Exint_IrqHandler(ExintInstanceIndexExint27);
00507     }
00508 #endif 
00509 #if(PDL_INTERRUPT_ENABLE_EXINT28 == PDL_ON)
00510     if(0 != bFM0P_INTREQ_IRQ05MON_EXTINT28)
00511     {
00512         Exint_IrqHandler(ExintInstanceIndexExint28);
00513     }
00514 #endif 
00515 #if(PDL_INTERRUPT_ENABLE_EXINT29 == PDL_ON)
00516     if(0 != bFM0P_INTREQ_IRQ05MON_EXTINT29)
00517     {
00518         Exint_IrqHandler(ExintInstanceIndexExint29);
00519     }
00520 #endif 
00521 #if(PDL_INTERRUPT_ENABLE_EXINT30 == PDL_ON)
00522     if(0 != bFM0P_INTREQ_IRQ05MON_EXTINT30)
00523     {
00524         Exint_IrqHandler(ExintInstanceIndexExint30);
00525     }
00526 #endif 
00527 #if(PDL_INTERRUPT_ENABLE_EXINT31 == PDL_ON)
00528     if(0 != bFM0P_INTREQ_IRQ05MON_EXTINT31)
00529     {
00530         Exint_IrqHandler(ExintInstanceIndexExint31);
00531     }
00532 #endif       
00533 }
00534 #endif
00535 
00536 /******************************************************************************/
00537 /*********************************** MFT **************************************/
00538 /******************************************************************************/
00539 #if (PDL_INTERRUPT_ENABLE_MFT0_FRT == PDL_ON) || \
00540     (PDL_INTERRUPT_ENABLE_MFT1_FRT == PDL_ON) || \
00541     (PDL_INTERRUPT_ENABLE_MFT2_FRT == PDL_ON)  
00542 
00547 void MFT_FRT_IRQHandler(void)
00548 { 
00549     uint32_t u32IrqMon = FM0P_INTREQ->IRQ28MON;
00550 #if (PDL_INTERRUPT_ENABLE_MFT0_FRT == PDL_ON)    
00551     if(0 != (u32IrqMon & 0x0000003Fu))
00552     {
00553         Mft_Frt_IrqHandler((volatile stc_mftn_frt_t*)&MFT0_FRT, &m_astcMftFrtInstanceDataLut[FrtInstanceIndexFrt0].stcInternData);
00554     }
00555 #endif   
00556 #if (PDL_INTERRUPT_ENABLE_MFT1_FRT == PDL_ON)    
00557     if(0 != (u32IrqMon & 0x00000FC0u))
00558     {
00559         Mft_Frt_IrqHandler((volatile stc_mftn_frt_t*)&MFT1_FRT, &m_astcMftFrtInstanceDataLut[FrtInstanceIndexFrt1].stcInternData);
00560     }
00561 #endif     
00562 #if (PDL_INTERRUPT_ENABLE_MFT2_FRT == PDL_ON)    
00563     if(0 != (u32IrqMon & 0x0003F000u))
00564     {
00565         Mft_Frt_IrqHandler((volatile stc_mftn_frt_t*)&MFT2_FRT, &m_astcMftFrtInstanceDataLut[FrtInstanceIndexFrt2].stcInternData);
00566     }
00567 #endif      
00568 }
00569 #endif
00570 
00571 #if (PDL_INTERRUPT_ENABLE_MFT0_OCU == PDL_ON) || \
00572     (PDL_INTERRUPT_ENABLE_MFT1_OCU == PDL_ON) || \
00573     (PDL_INTERRUPT_ENABLE_MFT2_OCU == PDL_ON)  
00574 
00579 void MFT_OPC_IRQHandler(void)
00580 {
00581     uint32_t u32IrqMon = FM0P_INTREQ->IRQ30MON;
00582     
00583 #if (PDL_INTERRUPT_ENABLE_MFT0_OCU == PDL_ON)    
00584     if(0 != (u32IrqMon & 0x0000003Fu))
00585     {
00586         Mft_Ocu_IrqHandler((volatile stc_mftn_ocu_t*)&MFT0_OCU, &m_astcMftOcuInstanceDataLut[OcuInstanceIndexOcu0].stcInternData);
00587     }
00588 #endif  
00589 #if (PDL_INTERRUPT_ENABLE_MFT1_OCU == PDL_ON)    
00590     if(0 != (u32IrqMon & 0x00000FC0u))
00591     {
00592         Mft_Ocu_IrqHandler((volatile stc_mftn_ocu_t*)&MFT1_OCU, &m_astcMftOcuInstanceDataLut[OcuInstanceIndexOcu1].stcInternData);
00593     }
00594 #endif     
00595 #if (PDL_INTERRUPT_ENABLE_MFT2_OCU == PDL_ON)    
00596     if(0 != (u32IrqMon & 0x00000FC0u))
00597     {
00598         Mft_Ocu_IrqHandler((volatile stc_mftn_ocu_t*)&MFT2_OCU, &m_astcMftOcuInstanceDataLut[OcuInstanceIndexOcu2].stcInternData);
00599     }
00600 #endif   
00601 }
00602 #endif
00603 
00604 #if (PDL_INTERRUPT_ENABLE_MFT0_WFG == PDL_ON) || \
00605     (PDL_INTERRUPT_ENABLE_MFT1_WFG == PDL_ON) || \
00606     (PDL_INTERRUPT_ENABLE_MFT2_WFG == PDL_ON)  
00607 
00612 void MFT_WFG_IRQHandler(void)
00613 {
00614     uint32_t u32IrqMon = FM0P_INTREQ->IRQ03MON;
00615       
00616 #if (PDL_INTERRUPT_ENABLE_MFT0_WFG == PDL_ON)
00617     if(0 != (u32IrqMon & 0x0000000Fu))
00618     {
00619         Mft_Wfg_IrqHandler((volatile stc_mftn_wfg_t*)&MFT0_WFG, &m_astcMftWfgInstanceDataLut[WfgInstanceIndexWfg0].stcInternData);
00620     }
00621 #endif
00622 #if (PDL_INTERRUPT_ENABLE_MFT1_WFG == PDL_ON)
00623     if(0 != (u32IrqMon & 0x000000F0u))
00624     {
00625         Mft_Wfg_IrqHandler((volatile stc_mftn_wfg_t*)&MFT1_WFG, &m_astcMftWfgInstanceDataLut[WfgInstanceIndexWfg1].stcInternData);
00626     }
00627 #endif    
00628 #if (PDL_INTERRUPT_ENABLE_MFT2_WFG == PDL_ON)
00629     if(0 != (u32IrqMon & 0x00000F00u))
00630     {
00631         Mft_Wfg_IrqHandler((volatile stc_mftn_wfg_t*)&MFT2_WFG, &m_astcMftWfgInstanceDataLut[WfgInstanceIndexWfg2].stcInternData);
00632     }
00633 #endif     
00634 }
00635 #endif
00636 
00637 #if (PDL_INTERRUPT_ENABLE_MFT0_ICU == PDL_ON) || \
00638     (PDL_INTERRUPT_ENABLE_MFT1_ICU == PDL_ON) || \
00639     (PDL_INTERRUPT_ENABLE_MFT2_ICU == PDL_ON)
00640 
00645 void MFT_IPC_IRQHandler(void)
00646 {
00647     uint32_t u32IrqMon = FM0P_INTREQ->IRQ29MON;
00648     
00649 #if (PDL_INTERRUPT_ENABLE_MFT0_ICU == PDL_ON)  
00650     if(0 != (u32IrqMon & 0x0000000Fu))
00651     {
00652         Mft_Icu_IrqHandler((volatile stc_mftn_icu_t*)&MFT0_ICU, &m_astcMftIcuInstanceDataLut[IcuInstanceIndexIcu0].stcInternData);
00653     }
00654 #endif    
00655 #if (PDL_INTERRUPT_ENABLE_MFT1_ICU == PDL_ON)  
00656     if(0 != (u32IrqMon & 0x000000F0u))
00657     {
00658         Mft_Icu_IrqHandler((volatile stc_mftn_icu_t*)&MFT1_ICU, &m_astcMftIcuInstanceDataLut[IcuInstanceIndexIcu1].stcInternData);
00659     }
00660 #endif    
00661 #if (PDL_INTERRUPT_ENABLE_MFT2_ICU == PDL_ON)  
00662     if(0 != (u32IrqMon & 0x00000F00u))
00663     {
00664         Mft_Icu_IrqHandler((volatile stc_mftn_icu_t*)&MFT2_ICU, &m_astcMftIcuInstanceDataLut[IcuInstanceIndexIcu2].stcInternData);
00665     }
00666 #endif      
00667 }
00668 #endif
00669 
00670 /******************************************************************************/
00671 /*********************************** PPG **************************************/
00672 /******************************************************************************/
00673 #if (PDL_INTERRUPT_ENABLE_PPG == PDL_ON)
00674 
00679 void PPG_IRQHandler(void)
00680 {
00681     Ppg_IrqHandler();
00682 }
00683 #endif
00684 
00685 /******************************************************************************/
00686 /*********************************** MFS **************************************/
00687 /******************************************************************************/
00688 
00689 #if (PDL_INTERRUPT_ENABLE_MFS0 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS8 == PDL_ON)
00690 
00695 void MFS0_8_RX_IRQHandler(void) 
00696 {
00697 #if (PDL_INTERRUPT_ENABLE_MFS0 == PDL_ON)    
00698     if(0 != bFM0P_INTREQ_IRQ07MON_MFSINT0)
00699     {
00700         switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData.enMode)
00701         {
00702             case MfsUartMode:
00703                 MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData));
00704                 break;
00705             case MfsCsioMode:
00706                 MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData));
00707                 break;          
00708             case MfsI2cMode:
00709                 MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData));
00710                 break;          
00711             case MfsLinMode:
00712                 MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData));
00713                 break;
00714             default:
00715                 break;
00716         
00717         }
00718     }
00719 #endif
00720 #if (PDL_INTERRUPT_ENABLE_MFS8 == PDL_ON)        
00721     if(0 != bFM0P_INTREQ_IRQ07MON_MFSINT1)
00722     {
00723         switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs8].stcInternData.enMode)
00724         {
00725             case MfsUartMode:
00726                 MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART8, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs8].stcInternData));
00727                 break;
00728             case MfsCsioMode:
00729                 MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO8, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs8].stcInternData));
00730                 break;          
00731             case MfsI2cMode:
00732                 MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C8, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs8].stcInternData));
00733                 break;          
00734             case MfsLinMode:
00735                 MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN8, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs8].stcInternData));
00736                 break;
00737             default:
00738                 break;
00739         
00740         }
00741     }
00742 #endif    
00743 }
00744 
00750 void MFS0_8_TX_IRQHandler(void)
00751 {
00752 #if (PDL_INTERRUPT_ENABLE_MFS0 == PDL_ON)    
00753     if(0 != bFM0P_INTREQ_IRQ08MON_MFSINT0)
00754     {
00755         switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData.enMode)
00756         {
00757             case MfsUartMode:
00758                 MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData));
00759                 break;
00760             case MfsCsioMode:
00761                 MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData));
00762                 break;          
00763             case MfsI2cMode:
00764                 MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData));
00765                 break;          
00766             case MfsLinMode:
00767                 MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData));
00768                 break;
00769             default:
00770                 break;
00771         
00772         }
00773     }
00774     if(0 != bFM0P_INTREQ_IRQ08MON_MFSINT1)
00775     {
00776        switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData.enMode)
00777         {
00778             case MfsUartMode:
00779                 break;
00780             case MfsCsioMode:
00781                 MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData));
00782                 break;          
00783             case MfsI2cMode:
00784                 MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData));
00785                 break;          
00786             case MfsLinMode:
00787                 MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData));
00788                 break;
00789             default:
00790                 break;
00791         
00792         }
00793     }
00794 #endif
00795 #if (PDL_INTERRUPT_ENABLE_MFS8 == PDL_ON)        
00796     if(0 != bFM0P_INTREQ_IRQ08MON_MFSINT2)
00797     {
00798         switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs8].stcInternData.enMode)
00799         {
00800             case MfsUartMode:
00801                 MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART8, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs8].stcInternData));
00802                 break;
00803             case MfsCsioMode:
00804                 MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO8, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs8].stcInternData));
00805                 break;          
00806             case MfsI2cMode:
00807                 MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C8, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs8].stcInternData));
00808                 break;          
00809             case MfsLinMode:
00810                 MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN8, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs8].stcInternData));
00811                 break;
00812             default:
00813                 break;
00814         
00815         }
00816     }
00817     if(0 != bFM0P_INTREQ_IRQ08MON_MFSINT3)
00818     {
00819         switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs8].stcInternData.enMode)
00820         {
00821             case MfsUartMode:
00822                 break;
00823             case MfsCsioMode:
00824                 MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO8, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs8].stcInternData));
00825                 break;          
00826             case MfsI2cMode:
00827                 MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C8, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs8].stcInternData));
00828                 break;          
00829             case MfsLinMode:
00830                 MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN8, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs8].stcInternData));
00831                 break;
00832             default:
00833                 break;
00834         
00835         } 
00836     }
00837 #endif    
00838 }
00839 #endif // #if (PDL_INTERRUPT_ENABLE_MFS0 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS8 == PDL_ON)
00840 
00841 #if (PDL_INTERRUPT_ENABLE_MFS1 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS9 == PDL_ON)
00842 
00847 void MFS1_9_RX_IRQHandler(void)
00848 {
00849 #if (PDL_INTERRUPT_ENABLE_MFS1 == PDL_ON)    
00850     if(0 != bFM0P_INTREQ_IRQ09MON_MFSINT0)
00851     {
00852         switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData.enMode)
00853         {
00854             case MfsUartMode:
00855                 MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData));
00856                 break;
00857             case MfsCsioMode:
00858                 MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData));
00859                 break;          
00860             case MfsI2cMode:
00861                 MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData));
00862                 break;          
00863             case MfsLinMode:
00864                 MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData));
00865                 break;
00866             default:
00867                 break;
00868         
00869         }
00870     }
00871 #endif
00872 #if (PDL_INTERRUPT_ENABLE_MFS9 == PDL_ON)        
00873     if(0 != bFM0P_INTREQ_IRQ09MON_MFSINT1)
00874     {
00875         switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs9].stcInternData.enMode)
00876         {
00877             case MfsUartMode:
00878                 MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART9, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs9].stcInternData));
00879                 break;
00880             case MfsCsioMode:
00881                 MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO9, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs9].stcInternData));
00882                 break;          
00883             case MfsI2cMode:
00884                 MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C9, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs9].stcInternData));
00885                 break;          
00886             case MfsLinMode:
00887                 MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN9, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs9].stcInternData));
00888                 break;
00889             default:
00890                 break;
00891         
00892         }
00893     }
00894 #endif    
00895 }
00896 
00902 void MFS1_9_TX_IRQHandler(void)
00903 {
00904 #if (PDL_INTERRUPT_ENABLE_MFS1 == PDL_ON)    
00905     if(0 != bFM0P_INTREQ_IRQ10MON_MFSINT0)
00906     {
00907         switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData.enMode)
00908         {
00909             case MfsUartMode:
00910                 MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData));
00911                 break;
00912             case MfsCsioMode:
00913                 MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData));
00914                 break;          
00915             case MfsI2cMode:
00916                 MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData));
00917                 break;          
00918             case MfsLinMode:
00919                 MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData));
00920                 break;
00921             default:
00922                 break;
00923         
00924         }
00925     }
00926     if(0 != bFM0P_INTREQ_IRQ10MON_MFSINT1)
00927     {
00928         switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData.enMode)
00929         {
00930             case MfsUartMode:
00931                 break;
00932             case MfsCsioMode:
00933                 MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData));
00934                 break;          
00935             case MfsI2cMode:
00936                 MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData));
00937                 break;          
00938             case MfsLinMode:
00939                 MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData));
00940                 break;
00941             default:
00942                 break;
00943         
00944         } 
00945     }
00946 #endif
00947 #if (PDL_INTERRUPT_ENABLE_MFS9 == PDL_ON)        
00948     if(0 != bFM0P_INTREQ_IRQ10MON_MFSINT2)
00949     {
00950         switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs9].stcInternData.enMode)
00951         {
00952             case MfsUartMode:
00953                 MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART9, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs9].stcInternData));
00954                 break;
00955             case MfsCsioMode:
00956                 MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO9, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs9].stcInternData));
00957                 break;          
00958             case MfsI2cMode:
00959                 MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C9, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs9].stcInternData));
00960                 break;          
00961             case MfsLinMode:
00962                 MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN9, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs9].stcInternData));
00963                 break;
00964             default:
00965                 break;
00966         
00967         }
00968     }
00969     if(0 != bFM0P_INTREQ_IRQ10MON_MFSINT3)
00970     {
00971         switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs9].stcInternData.enMode)
00972         {
00973             case MfsUartMode:
00974                 break;
00975             case MfsCsioMode:
00976                 MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO9, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs9].stcInternData));
00977                 break;          
00978             case MfsI2cMode:
00979                 MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C9, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs9].stcInternData));
00980                 break;          
00981             case MfsLinMode:
00982                 MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN9, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs9].stcInternData));
00983                 break;
00984             default:
00985                 break;
00986         
00987         }
00988     }
00989 #endif    
00990 }
00991 #endif // #if (PDL_INTERRUPT_ENABLE_MFS1 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS9 == PDL_ON)
00992 
00993 #if (PDL_INTERRUPT_ENABLE_MFS2 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS10 == PDL_ON)
00994 
00999 void MFS2_10_RX_IRQHandler(void)
01000 {
01001 #if (PDL_INTERRUPT_ENABLE_MFS2 == PDL_ON)    
01002     if(0 != bFM0P_INTREQ_IRQ11MON_MFSINT0)
01003     {
01004         switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData.enMode)
01005         {
01006             case MfsUartMode:
01007                 MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData));
01008                 break;
01009             case MfsCsioMode:
01010                 MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData));
01011                 break;          
01012             case MfsI2cMode:
01013                 MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData));
01014                 break;          
01015             case MfsLinMode:
01016                 MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData));
01017                 break;
01018             default:
01019                 break;
01020         
01021         } 
01022     }
01023 #endif
01024 #if (PDL_INTERRUPT_ENABLE_MFS10 == PDL_ON)        
01025     if(0 != bFM0P_INTREQ_IRQ11MON_MFSINT1)
01026     {
01027         switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs10].stcInternData.enMode)
01028         {
01029             case MfsUartMode:
01030                 MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART10, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs10].stcInternData));
01031                 break;
01032             case MfsCsioMode:
01033                 MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO10, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs10].stcInternData));
01034                 break;          
01035             case MfsI2cMode:
01036                 MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C10, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs10].stcInternData));
01037                 break;          
01038             case MfsLinMode:
01039                 MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN10, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs10].stcInternData));
01040                 break;
01041             default:
01042                 break;
01043         
01044         } 
01045     }
01046 #endif    
01047 }
01048 
01054 void MFS2_10_TX_IRQHandler(void)
01055 {
01056 #if (PDL_INTERRUPT_ENABLE_MFS2 == PDL_ON)    
01057     if(0 != bFM0P_INTREQ_IRQ12MON_MFSINT0)
01058     {
01059         switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData.enMode)
01060         {
01061             case MfsUartMode:
01062                 MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData));
01063                 break;
01064             case MfsCsioMode:
01065                 MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData));
01066                 break;          
01067             case MfsI2cMode:
01068                 MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData));
01069                 break;          
01070             case MfsLinMode:
01071                 MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData));
01072                 break;
01073             default:
01074                 break;
01075         
01076         }
01077     }
01078     if(0 != bFM0P_INTREQ_IRQ12MON_MFSINT1)
01079     {
01080         switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData.enMode)
01081         {
01082             case MfsUartMode:
01083                 break;
01084             case MfsCsioMode:
01085                 MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData));
01086                 break;          
01087             case MfsI2cMode:
01088                 MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData));
01089                 break;          
01090             case MfsLinMode:
01091                 MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData));
01092                 break;
01093             default:
01094                 break;
01095         
01096         } 
01097     }
01098 #endif
01099 #if (PDL_INTERRUPT_ENABLE_MFS10 == PDL_ON)        
01100     if(0 != bFM0P_INTREQ_IRQ12MON_MFSINT2)
01101     {
01102         switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs10].stcInternData.enMode)
01103         {
01104             case MfsUartMode:
01105                 MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART10, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs10].stcInternData));
01106                 break;
01107             case MfsCsioMode:
01108                 MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO10, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs10].stcInternData));
01109                 break;          
01110             case MfsI2cMode:
01111                 MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C10, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs10].stcInternData));
01112                 break;          
01113             case MfsLinMode:
01114                 MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN10, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs10].stcInternData));
01115                 break;
01116             default:
01117                 break;
01118         
01119         }
01120     }
01121     if(0 != bFM0P_INTREQ_IRQ12MON_MFSINT3)
01122     {
01123         switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs10].stcInternData.enMode)
01124         {
01125             case MfsUartMode:
01126                 break;
01127             case MfsCsioMode:
01128                 MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO10, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs10].stcInternData));
01129                 break;          
01130             case MfsI2cMode:
01131                 MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C10, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs10].stcInternData));
01132                 break;          
01133             case MfsLinMode:
01134                 MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN10, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs10].stcInternData));
01135                 break;
01136             default:
01137                 break;
01138         
01139         }
01140     }
01141 #endif    
01142 }
01143 #endif // #if (PDL_INTERRUPT_ENABLE_MFS2 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS10 == PDL_ON)
01144 
01145 #if (PDL_INTERRUPT_ENABLE_MFS3 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS11 == PDL_ON)
01146 
01151 void MFS3_11_RX_IRQHandler(void)
01152 {
01153 #if (PDL_INTERRUPT_ENABLE_MFS3 == PDL_ON)    
01154     if(0 != bFM0P_INTREQ_IRQ13MON_MFSINT0)
01155     {
01156         switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData.enMode)
01157         {
01158             case MfsUartMode:
01159                 MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData));
01160                 break;
01161             case MfsCsioMode:
01162                 MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData));
01163                 break;          
01164             case MfsI2cMode:
01165                 MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData));
01166                 break;          
01167             case MfsLinMode:
01168                 MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData));
01169                 break;
01170             default:
01171                 break;
01172         
01173         } 
01174     }
01175 #endif
01176 #if (PDL_INTERRUPT_ENABLE_MFS11 == PDL_ON)        
01177     if(0 != bFM0P_INTREQ_IRQ13MON_MFSINT1)
01178     {
01179         switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs11].stcInternData.enMode)
01180         {
01181             case MfsUartMode:
01182                 MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART11, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs11].stcInternData));
01183                 break;
01184             case MfsCsioMode:
01185                 MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO11, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs11].stcInternData));
01186                 break;          
01187             case MfsI2cMode:
01188                 MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C11, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs11].stcInternData));
01189                 break;          
01190             case MfsLinMode:
01191                 MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN11, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs11].stcInternData));
01192                 break;
01193             default:
01194                 break;
01195         
01196         } 
01197     }
01198 #endif    
01199 }
01200 
01206 void MFS3_11_TX_IRQHandler(void)
01207 {
01208 #if (PDL_INTERRUPT_ENABLE_MFS3 == PDL_ON)    
01209     if(0 != bFM0P_INTREQ_IRQ14MON_MFSINT0)
01210     {
01211         switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData.enMode)
01212         {
01213             case MfsUartMode:
01214                 MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData));
01215                 break;
01216             case MfsCsioMode:
01217                 MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData));
01218                 break;          
01219             case MfsI2cMode:
01220                 MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData));
01221                 break;          
01222             case MfsLinMode:
01223                 MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData));
01224                 break;
01225             default:
01226                 break;
01227         
01228         }
01229     }
01230     if(0 != bFM0P_INTREQ_IRQ14MON_MFSINT1)
01231     {
01232         switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData.enMode)
01233         {
01234             case MfsUartMode:
01235                 break;
01236             case MfsCsioMode:
01237                 MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData));
01238                 break;          
01239             case MfsI2cMode:
01240                 MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData));
01241                 break;          
01242             case MfsLinMode:
01243                 MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData));
01244                 break;
01245             default:
01246                 break;
01247         
01248         }
01249     }
01250 #endif
01251 #if (PDL_INTERRUPT_ENABLE_MFS11 == PDL_ON)        
01252     if(0 != bFM0P_INTREQ_IRQ14MON_MFSINT2)
01253     {
01254         switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs11].stcInternData.enMode)
01255         {
01256             case MfsUartMode:
01257                 MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART11, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs11].stcInternData));
01258                 break;
01259             case MfsCsioMode:
01260                 MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO11, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs11].stcInternData));
01261                 break;          
01262             case MfsI2cMode:
01263                 MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C11, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs11].stcInternData));
01264                 break;          
01265             case MfsLinMode:
01266                 MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN11, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs11].stcInternData));
01267                 break;
01268             default:
01269                 break;
01270         
01271         }
01272     }
01273     if(0 != bFM0P_INTREQ_IRQ14MON_MFSINT3)
01274     {
01275         switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs11].stcInternData.enMode)
01276         {
01277             case MfsUartMode:
01278                 break;
01279             case MfsCsioMode:
01280                 MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO11, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs11].stcInternData));
01281                 break;          
01282             case MfsI2cMode:
01283                 MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C11, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs11].stcInternData));
01284                 break;          
01285             case MfsLinMode:
01286                 MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN11, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs11].stcInternData));
01287                 break;
01288             default:
01289                 break;
01290         
01291         }
01292     }
01293 #endif    
01294 }
01295 #endif // #if (PDL_INTERRUPT_ENABLE_MFS3 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS11 == PDL_ON)
01296 
01297 #if (PDL_INTERRUPT_ENABLE_MFS4 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS12 == PDL_ON)
01298 
01303 void MFS4_12_RX_IRQHandler(void)
01304 {
01305 #if (PDL_INTERRUPT_ENABLE_MFS4 == PDL_ON)    
01306     if(0 != bFM0P_INTREQ_IRQ15MON_MFSINT0)
01307     {
01308         switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData.enMode)
01309         {
01310             case MfsUartMode:
01311                 MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData));
01312                 break;
01313             case MfsCsioMode:
01314                 MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData));
01315                 break;          
01316             case MfsI2cMode:
01317                 MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData));
01318                 break;          
01319             case MfsLinMode:
01320                 MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData));
01321                 break;
01322             default:
01323                 break;
01324         
01325         } 
01326     }
01327 #endif
01328 #if (PDL_INTERRUPT_ENABLE_MFS12 == PDL_ON)        
01329     if(0 != bFM0P_INTREQ_IRQ15MON_MFSINT1)
01330     {
01331         switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs12].stcInternData.enMode)
01332         {
01333             case MfsUartMode:
01334                 MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART12, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs12].stcInternData));
01335                 break;
01336             case MfsCsioMode:
01337                 MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO12, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs12].stcInternData));
01338                 break;          
01339             case MfsI2cMode:
01340                 MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C12, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs12].stcInternData));
01341                 break;          
01342             case MfsLinMode:
01343                 MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN12, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs12].stcInternData));
01344                 break;
01345             default:
01346                 break;
01347         
01348         }  
01349     }
01350 #endif    
01351 }
01352 
01358 void MFS4_12_TX_IRQHandler(void)
01359 {
01360 #if (PDL_INTERRUPT_ENABLE_MFS4 == PDL_ON)    
01361     if(0 != bFM0P_INTREQ_IRQ16MON_MFSINT0)
01362     {
01363         switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData.enMode)
01364         {
01365             case MfsUartMode:
01366                 MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData));
01367                 break;
01368             case MfsCsioMode:
01369                 MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData));
01370                 break;          
01371             case MfsI2cMode:
01372                 MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData));
01373                 break;          
01374             case MfsLinMode:
01375                 MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData));
01376                 break;
01377             default:
01378                 break;
01379         }
01380     }
01381     if(0 != bFM0P_INTREQ_IRQ16MON_MFSINT1)
01382     {
01383         switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData.enMode)
01384         {
01385             case MfsUartMode:
01386                 break;
01387             case MfsCsioMode:
01388                 MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData));
01389                 break;          
01390             case MfsI2cMode:
01391                 MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData));
01392                 break;          
01393             case MfsLinMode:
01394                 MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData));
01395                 break;
01396             default:
01397                 break;
01398         
01399         }
01400     }
01401 #endif
01402 #if (PDL_INTERRUPT_ENABLE_MFS12 == PDL_ON)        
01403     if(0 != bFM0P_INTREQ_IRQ16MON_MFSINT2)
01404     {
01405         switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs12].stcInternData.enMode)
01406         {
01407             case MfsUartMode:
01408                 MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART12, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs12].stcInternData));
01409                 break;
01410             case MfsCsioMode:
01411                 MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO12, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs12].stcInternData));
01412                 break;          
01413             case MfsI2cMode:
01414                 MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C12, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs12].stcInternData));
01415                 break;          
01416             case MfsLinMode:
01417                 MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN12, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs12].stcInternData));
01418                 break;
01419             default:
01420                 break;
01421         }
01422     }
01423     if(0 != bFM0P_INTREQ_IRQ16MON_MFSINT3)
01424     {
01425         switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs12].stcInternData.enMode)
01426         {
01427             case MfsUartMode:
01428                 break;
01429             case MfsCsioMode:
01430                 MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO12, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs12].stcInternData));
01431                 break;          
01432             case MfsI2cMode:
01433                 MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C12, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs12].stcInternData));
01434                 break;          
01435             case MfsLinMode:
01436                 MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN12, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs12].stcInternData));
01437                 break;
01438             default:
01439                 break;
01440         
01441         }
01442     }
01443 #endif    
01444 }
01445 #endif // #if (PDL_INTERRUPT_ENABLE_MFS4 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS12 == PDL_ON)
01446 
01447 #if (PDL_INTERRUPT_ENABLE_MFS5 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS13 == PDL_ON)
01448 
01453 void MFS5_13_RX_IRQHandler(void)
01454 {
01455 #if (PDL_INTERRUPT_ENABLE_MFS5 == PDL_ON)    
01456     if(0 != bFM0P_INTREQ_IRQ17MON_MFSINT0)
01457     {
01458         switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData.enMode)
01459         {
01460             case MfsUartMode:
01461                 MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData));
01462                 break;
01463             case MfsCsioMode:
01464                 MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData));
01465                 break;          
01466             case MfsI2cMode:
01467                 MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData));
01468                 break;          
01469             case MfsLinMode:
01470                 MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData));
01471                 break;
01472             default:
01473                 break;
01474         
01475         }  
01476     }
01477 #endif
01478 #if (PDL_INTERRUPT_ENABLE_MFS13 == PDL_ON)        
01479     if(0 != bFM0P_INTREQ_IRQ17MON_MFSINT1)
01480     {
01481         switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs13].stcInternData.enMode)
01482         {
01483             case MfsUartMode:
01484                 MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART13, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs13].stcInternData));
01485                 break;
01486             case MfsCsioMode:
01487                 MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO13, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs13].stcInternData));
01488                 break;          
01489             case MfsI2cMode:
01490                 MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C13, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs13].stcInternData));
01491                 break;          
01492             case MfsLinMode:
01493                 MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN13, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs13].stcInternData));
01494                 break;
01495             default:
01496                 break;
01497         
01498         }  
01499     }
01500 #endif    
01501 }
01502 
01508 void MFS5_13_TX_IRQHandler(void)
01509 {
01510 #if (PDL_INTERRUPT_ENABLE_MFS5 == PDL_ON)    
01511     if(0 != bFM0P_INTREQ_IRQ18MON_MFSINT0)
01512     {
01513         switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData.enMode)
01514         {
01515             case MfsUartMode:
01516                 MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData));
01517                 break;
01518             case MfsCsioMode:
01519                 MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData));
01520                 break;          
01521             case MfsI2cMode:
01522                 MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData));
01523                 break;          
01524             case MfsLinMode:
01525                 MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData));
01526                 break;
01527             default:
01528                 break;
01529         }
01530     }
01531     if(0 != bFM0P_INTREQ_IRQ18MON_MFSINT1)
01532     {
01533         switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData.enMode)
01534         {
01535             case MfsUartMode:
01536                 break;
01537             case MfsCsioMode:
01538                 MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData));
01539                 break;          
01540             case MfsI2cMode:
01541                 MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData));
01542                 break;          
01543             case MfsLinMode:
01544                 MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData));
01545                 break;
01546             default:
01547                 break;
01548         
01549         } 
01550     }
01551 #endif
01552 #if (PDL_INTERRUPT_ENABLE_MFS13 == PDL_ON)        
01553     if(0 != bFM0P_INTREQ_IRQ18MON_MFSINT2)
01554     {
01555         switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs13].stcInternData.enMode)
01556         {
01557             case MfsUartMode:
01558                 MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART13, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs13].stcInternData));
01559                 break;
01560             case MfsCsioMode:
01561                 MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO13, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs13].stcInternData));
01562                 break;          
01563             case MfsI2cMode:
01564                 MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C13, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs13].stcInternData));
01565                 break;          
01566             case MfsLinMode:
01567                 MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN13, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs13].stcInternData));
01568                 break;
01569             default:
01570                 break;
01571         }
01572     }
01573     if(0 != bFM0P_INTREQ_IRQ18MON_MFSINT3)
01574     {
01575         switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs13].stcInternData.enMode)
01576         {
01577             case MfsUartMode:
01578                 break;
01579             case MfsCsioMode:
01580                 MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO13, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs13].stcInternData));
01581                 break;          
01582             case MfsI2cMode:
01583                 MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C13, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs13].stcInternData));
01584                 break;          
01585             case MfsLinMode:
01586                 MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN13, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs13].stcInternData));
01587                 break;
01588             default:
01589                 break;
01590         
01591         }
01592     }
01593 #endif    
01594 }
01595 #endif // #if (PDL_INTERRUPT_ENABLE_MFS5 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS13 == PDL_ON)
01596 
01597 #if (PDL_INTERRUPT_ENABLE_MFS6 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS14 == PDL_ON) ||  \
01598     (PDL_INTERRUPT_ENABLE_DMA0 == PDL_ON) || (PDL_INTERRUPT_ENABLE_DMA1 == PDL_ON)   
01599 
01604 void MFS6_14_RX_DMA0_IRQHandler(void)
01605 {
01606 #if (PDL_INTERRUPT_ENABLE_MFS6 == PDL_ON)    
01607     if(0 != bFM0P_INTREQ_IRQ19MON_MFSINT0)
01608     {
01609         switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData.enMode)
01610         {
01611             case MfsUartMode:
01612                 MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData));
01613                 break;
01614             case MfsCsioMode:
01615                 MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData));
01616                 break;          
01617             case MfsI2cMode:
01618                 MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData));
01619                 break;          
01620             case MfsLinMode:
01621                 MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData));
01622                 break;
01623             default:
01624                 break;
01625         
01626         }  
01627     }
01628 #endif
01629 #if (PDL_INTERRUPT_ENABLE_MFS14 == PDL_ON)        
01630     if(0 != bFM0P_INTREQ_IRQ19MON_MFSINT1)
01631     {
01632         switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs14].stcInternData.enMode)
01633         {
01634             case MfsUartMode:
01635                 MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART14, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs14].stcInternData));
01636                 break;
01637             case MfsCsioMode:
01638                 MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO14, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs14].stcInternData));
01639                 break;          
01640             case MfsI2cMode:
01641                 MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C14, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs14].stcInternData));
01642                 break;          
01643             case MfsLinMode:
01644                 MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN14, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs14].stcInternData));
01645                 break;
01646             default:
01647                 break;
01648         
01649         }  
01650     }
01651 #endif    
01652 #if (PDL_INTERRUPT_ENABLE_DMA0 == PDL_ON)        
01653     if(0 != bFM0P_INTREQ_IRQ19MON_DMAINT0)
01654     {
01655         DmaIrqHandler(0);
01656     }
01657 #endif 
01658 }
01659 
01665 void MFS6_14_TX_DMA1_IRQHandler(void)
01666 {
01667 #if (PDL_INTERRUPT_ENABLE_MFS6 == PDL_ON)    
01668     if(0 != bFM0P_INTREQ_IRQ20MON_MFSINT0)
01669     {
01670         switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData.enMode)
01671         {
01672             case MfsUartMode:
01673                 MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData));
01674                 break;
01675             case MfsCsioMode:
01676                 MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData));
01677                 break;          
01678             case MfsI2cMode:
01679                 MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData));
01680                 break;          
01681             case MfsLinMode:
01682                 MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData));
01683                 break;
01684             default:
01685                 break;
01686         }
01687     }
01688     if(0 != bFM0P_INTREQ_IRQ20MON_MFSINT1)
01689     {
01690         switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData.enMode)
01691         {
01692             case MfsUartMode:
01693                 break;
01694             case MfsCsioMode:
01695                 MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData));
01696                 break;          
01697             case MfsI2cMode:
01698                 MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData));
01699                 break;          
01700             case MfsLinMode:
01701                 MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData));
01702                 break;
01703             default:
01704                 break;
01705         
01706         } 
01707     }
01708 #endif
01709 #if (PDL_INTERRUPT_ENABLE_MFS14 == PDL_ON)        
01710     if(0 != bFM0P_INTREQ_IRQ20MON_MFSINT2)
01711     {
01712         switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs14].stcInternData.enMode)
01713         {
01714             case MfsUartMode:
01715                 MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART14, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs14].stcInternData));
01716                 break;
01717             case MfsCsioMode:
01718                 MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO14, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs14].stcInternData));
01719                 break;          
01720             case MfsI2cMode:
01721                 MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C14, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs14].stcInternData));
01722                 break;          
01723             case MfsLinMode:
01724                 MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN14, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs14].stcInternData));
01725                 break;
01726             default:
01727                 break;
01728         }
01729     }
01730     if(0 != bFM0P_INTREQ_IRQ20MON_MFSINT3)
01731     {
01732         switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs14].stcInternData.enMode)
01733         {
01734             case MfsUartMode:
01735                 break;
01736             case MfsCsioMode:
01737                 MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO14, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs14].stcInternData));
01738                 break;          
01739             case MfsI2cMode:
01740                 MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C14, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs14].stcInternData));
01741                 break;          
01742             case MfsLinMode:
01743                 MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN14, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs14].stcInternData));
01744                 break;
01745             default:
01746                 break;
01747         
01748         }
01749     }
01750 #endif    
01751 #if (PDL_INTERRUPT_ENABLE_DMA1 == PDL_ON)
01752     if(0 != bFM0P_INTREQ_IRQ20MON_DMAINT1)
01753     {
01754         DmaIrqHandler(1);
01755     }    
01756 #endif    
01757     
01758 }
01759 #endif // #if (PDL_INTERRUPT_ENABLE_MFS6 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS14 == PDL_ON)
01760 
01761 #if (PDL_INTERRUPT_ENABLE_MFS7 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS15 == PDL_ON) || \
01762     (PDL_INTERRUPT_ENABLE_DMA2 == PDL_ON) || (PDL_INTERRUPT_ENABLE_DMA3 == PDL_ON) 
01763 
01769 void MFS7_15_RX_DMA2_IRQHandler(void)
01770 {
01771 #if (PDL_INTERRUPT_ENABLE_MFS7 == PDL_ON)    
01772     if(0 != bFM0P_INTREQ_IRQ21MON_MFSINT0)
01773     {
01774         switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData.enMode)
01775         {
01776             case MfsUartMode:
01777                 MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData));
01778                 break;
01779             case MfsCsioMode:
01780                 MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData));
01781                 break;          
01782             case MfsI2cMode:
01783                 MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData));
01784                 break;          
01785             case MfsLinMode:
01786                 MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData));
01787                 break;
01788             default:
01789                 break;
01790         
01791         }   
01792     }
01793 #endif
01794 #if (PDL_INTERRUPT_ENABLE_MFS15 == PDL_ON)        
01795     if(0 != bFM0P_INTREQ_IRQ21MON_MFSINT1)
01796     {
01797         switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs15].stcInternData.enMode)
01798         {
01799             case MfsUartMode:
01800                 MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART15, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs15].stcInternData));
01801                 break;
01802             case MfsCsioMode:
01803                 MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO15, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs15].stcInternData));
01804                 break;          
01805             case MfsI2cMode:
01806                 MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C15, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs15].stcInternData));
01807                 break;          
01808             case MfsLinMode:
01809                 MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN15, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs15].stcInternData));
01810                 break;
01811             default:
01812                 break;
01813         
01814         }   
01815     }
01816 #endif    
01817 #if (PDL_INTERRUPT_ENABLE_DMA2 == PDL_ON)        
01818     if(0 != bFM0P_INTREQ_IRQ21MON_DMAINT2)
01819     {
01820         DmaIrqHandler(2);
01821     }
01822 #endif 
01823 }
01824 
01830 void MFS7_15_TX_DMA3_IRQHandler(void)
01831 {
01832 #if (PDL_INTERRUPT_ENABLE_MFS7 == PDL_ON)    
01833     if(0 != bFM0P_INTREQ_IRQ22MON_MFSINT0)
01834     {
01835         switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData.enMode)
01836         {
01837             case MfsUartMode:
01838                 MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData));
01839                 break;
01840             case MfsCsioMode:
01841                 MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData));
01842                 break;          
01843             case MfsI2cMode:
01844                 MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData));
01845                 break;          
01846             case MfsLinMode:
01847                 MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData));
01848                 break;
01849             default:
01850                 break;
01851         }
01852     }
01853     if(0 != bFM0P_INTREQ_IRQ22MON_MFSINT1)
01854     {
01855         switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData.enMode)
01856         {
01857             case MfsUartMode:
01858                 break;
01859             case MfsCsioMode:
01860                 MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData));
01861                 break;          
01862             case MfsI2cMode:
01863                 MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData));
01864                 break;          
01865             case MfsLinMode:
01866                 MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData));
01867                 break;
01868             default:
01869                 break;
01870         
01871         }
01872     }
01873 #endif
01874 #if (PDL_INTERRUPT_ENABLE_MFS15 == PDL_ON)        
01875     if(0 != bFM0P_INTREQ_IRQ22MON_MFSINT2)
01876     {
01877         switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs15].stcInternData.enMode)
01878         {
01879             case MfsUartMode:
01880                 MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART15, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs15].stcInternData));
01881                 break;
01882             case MfsCsioMode:
01883                 MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO15, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs15].stcInternData));
01884                 break;          
01885             case MfsI2cMode:
01886                 MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C15, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs15].stcInternData));
01887                 break;          
01888             case MfsLinMode:
01889                 MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN15, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs15].stcInternData));
01890                 break;
01891             default:
01892                 break;
01893         }
01894     }
01895     if(0 != bFM0P_INTREQ_IRQ22MON_MFSINT3)
01896     {
01897         switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs15].stcInternData.enMode)
01898         {
01899             case MfsUartMode:
01900                 break;
01901             case MfsCsioMode:
01902                 MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO15, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs15].stcInternData));
01903                 break;          
01904             case MfsI2cMode:
01905                 MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C15, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs15].stcInternData));
01906                 break;          
01907             case MfsLinMode:
01908                 MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN15, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs15].stcInternData));
01909                 break;
01910             default:
01911                 break;
01912         
01913         }
01914     }
01915 #endif    
01916 #if (PDL_INTERRUPT_ENABLE_DMA3 == PDL_ON)
01917     if(0 != bFM0P_INTREQ_IRQ22MON_DMAINT3)
01918     {
01919         DmaIrqHandler(3);
01920     }    
01921 #endif    
01922     
01923 }
01924 #endif // #if (PDL_INTERRUPT_ENABLE_MFS7 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS15 == PDL_ON)
01925 
01926 /******************************************************************************/
01927 /* EOF (not truncated)                                                        */
01928 /******************************************************************************/